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package firrtlTests

import java.io._
import org.scalatest._
import org.scalatest.prop._
import firrtl.{Parser,Circuit}
import firrtl.passes._

class ChirrtlSpec extends FirrtlFlatSpec {

  "Chirrtl memories" should "allow ports with clocks defined after the memory" in {
    val passes = Seq(
      CInferTypes,
      CInferMDir,
      RemoveCHIRRTL,
      ToWorkingIR,            
      CheckHighForm,
      ResolveKinds,
      InferTypes,
      CheckTypes,
      ResolveGenders,
      CheckGenders,
      InferWidths,
      CheckWidths,
      PullMuxes,
      ExpandConnects,
      RemoveAccesses,
      ExpandWhens,
      CheckInitialization
    )
    val input =
     """circuit Unit :
       |  module Unit :
       |    input clk : Clock
       |    smem ram : UInt<32>[128]
       |    node newClock = clk
       |    infer mport x = ram[UInt(2)], newClock
       |    x <= UInt(3)
       |    when UInt(1) :
       |      infer mport y = ram[UInt(4)], newClock
       |      y <= UInt(5)
       """.stripMargin
    passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
      (c: Circuit, p: Pass) => p.run(c)
    }
  }

  it should "compile and run" in {
    runFirrtlTest("ChirrtlMems", "/features")
  }
}
