chisel6.4.0 < Back
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# Packages

-  package root
  Definition Classes
    root
-  package svsim
  Definition Classes
    root
-  object Backend
  Definition Classes
    svsim
- HarnessCompilationFlags
- Parameters

o

svsim.Backend

# HarnessCompilationFlags

###

#### object HarnessCompilationFlags

A namespace for flags affecting which code in the harness is compiled.

Source
  Backend.scala

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### Value Members

1.  final def !=(arg0: Any): Boolean
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2.  final def ##: Int
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3.  final def ==(arg0: Any): Boolean
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4.  final def asInstanceOf[T0]: T0
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5.  val backendEngagesInASLRShenanigans: String

   VCS first checks whether address-space layout randomization (ASLR) is enabled, and if it is, _helpfully_ relaunches this executable with ASLR disabled.

   VCS first checks whether address-space layout randomization (ASLR) is enabled, and if it is, _helpfully_ relaunches this executable with ASLR disabled. Unfortunately, this causes code executed prior to `simulation_main` to be executed twice, which is problematic, especially since we redirect `stdin` and `stdout`.

6.  def clone(): AnyRef
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     protected[lang]
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     @throws(classOf[java.lang.CloneNotSupportedException]) @native()
7.  val enableFsdbTracingSupport: String
8.  val enableVCSSupport: String

   This flag controls if VCS-specifc code is compiled.

9.  val enableVcdTracingSupport: String

   Flags enabling various tracing mechanisms.

   Flags enabling various tracing mechanisms. Note: These flags do not cause tracing to occur, they simply support for these tracing mechanisms in the harness.

10.  val enableVerilatorSupport: String

    Verilator support requires that we manually implement some SystemVerilog functions, such as `run_simulation` and `simulation_main`.

    Verilator support requires that we manually implement some SystemVerilog functions, such as `run_simulation` and `simulation_main`. These flags control the Verilator-specific code paths.

11.  val enableVerilatorTrace: String
12.  val enableVpdTracingSupport: String
13.  final def eq(arg0: AnyRef): Boolean
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14.  def equals(arg0: AnyRef): Boolean
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15.  def finalize(): Unit
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16.  final def getClass(): Class[_ <: AnyRef]
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      @native()
17.  def hashCode(): Int
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18.  final def isInstanceOf[T0]: Boolean
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19.  final def ne(arg0: AnyRef): Boolean
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20.  final def notify(): Unit
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      @native()
21.  final def notifyAll(): Unit
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22.  val supportsDelayInPublicFunctions: String

    Verilator does not currently support delay (`#delay`) in DPI functions, so we omit the SystemVerilog definition of the `run_simulation` function and instead provide a C implementation.

23.  final def synchronized[T0](arg0: => T0): T0
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24.  def toString(): String
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25.  final def wait(): Unit
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      @throws(classOf[java.lang.InterruptedException])
26.  final def wait(arg0: Long, arg1: Int): Unit
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      @throws(classOf[java.lang.InterruptedException])
27.  final def wait(arg0: Long): Unit
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      @throws(classOf[java.lang.InterruptedException]) @native()

### Inherited from AnyRef

### Inherited from Any

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