chisel6.4.0 < Back
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# Packages

-  package root
  Definition Classes
    root
-  package chisel3

  This package contains the main chisel3 API.

  This package contains the main chisel3 API.

  Definition Classes
    root
-  package aop
  Definition Classes
    chisel3
-  package choice

  This package contains Chisel language definitions for describing configuration options and their accepted values.

  This package contains Chisel language definitions for describing configuration options and their accepted values.

  Definition Classes
    chisel3
-  package connectable
  Definition Classes
    chisel3
-  package experimental

  Package for experimental features, which may have their API changed, be removed, etc.

  Package for experimental features, which may have their API changed, be removed, etc.

  Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.

  Definition Classes
    chisel3
-  package interface
  Definition Classes
    chisel3
-  package ltl
  Definition Classes
    chisel3
-  package naming
  Definition Classes
    chisel3
-  package probe
  Definition Classes
    chisel3
-  package properties

  The properties package includes functionality related to non-hardware data.

  The properties package includes functionality related to non-hardware data.

  This entire package is currently very experimental, so expect some rough edges and rapid API evolution.

  Definition Classes
    chisel3
-  package reflect
  Definition Classes
    chisel3
-  package simulator
  Definition Classes
    chisel3
-  package stage
  Definition Classes
    chisel3
-  package std
  Definition Classes
    chisel3
-  package testers

  The testers package provides the basic interface for chisel testers.

  The testers package provides the basic interface for chisel testers.

  Definition Classes
    chisel3
-  package util

  The util package provides extensions to core chisel for common hardware components and utility functions

  The util package provides extensions to core chisel for common hardware components and utility functions

  Definition Classes
    chisel3
- ActualDirection
- Aggregate
- AliasedAggregateFieldException
- AsyncReset
- AutoClonetypeException
- BiConnectException
- Binary
- BindingException
- Bits
- Bits
- BlackBox
- Bool
- Bool
- BoolFactory
- BuildInfo
- Bundle
- Character
- ChiselEnum
- ChiselException
- Clock
- Const
- Data
- Decimal
- Disable
- DontCare
- Element
- EnumType
- ExpectedAnnotatableException
- ExpectedChiselTypeException
- ExpectedHardwareException
- FirrtlFormat
- FixedIOBaseModule
- FixedIOExtModule
- FixedIORawModule
- FlatIO
- Flipped
- FullName
- HasTarget
- Hexadecimal
- IO
- IgnoreSeqInBundle
- ImplicitClock
- ImplicitReset
- Input
- InstanceId
- InternalErrorException
- KnownWidth
- Mem
- MemBase
- MixedDirectionAggregateException
- Module
- ModuleAspect
- MonoConnectException
- Mux
- Name
- Num
- NumObject
- Output
- PString
- Percent
- Printable
- PrintableHelper
- Printables
- RawModule
- RebindingException
- Record
- Reg
- RegInit
- RegNext
- RequireAsyncReset
- RequireSyncReset
- Reset
- ResetType
- SInt
- SInt
- SIntFactory
- SourceInfoDoc
- SpecifiedDirection
- SyncReadMem
- UInt
- UInt
- UIntFactory
- UnknownWidth
- Vec
- Vec
- VecFactory
- VecInit
- VecLike
- VerifPrintMacrosDoc
- VerificationStatement
- WhenContext
- Width
- Wire
- WireDefault
- WireFactory
- WireInit
- assert
- assume
- chiselTypeOf
- cover
- dontTouch
- emitVerilog
- fromBigIntToLiteral
- fromBooleanToLiteral
- fromIntToLiteral
- fromIntToWidth
- fromLongToLiteral
- fromStringToLiteral
- getVerilogString
- layer
- printf
- stop
- suppressEnumCastWarning
- when
- withClock
- withClockAndReset
- withDisable
- withReset
- withoutIO

c

chisel3

# MemBase

###

#### sealed abstract class MemBase[T <: Data] extends HasId with NamedComponent with SourceInfoDoc

Source
  Mem.scala

Linear Supertypes
SourceInfoDoc, NamedComponent, HasId, InstanceId, AnyRef, Any
Known Subclasses
Mem, SyncReadMem
Type Hierarchy

Ordering

1. Grouped
2. Alphabetic
3. By Inheritance

Inherited

1. MemBase
2. SourceInfoDoc
3. NamedComponent
4. HasId
5. InstanceId
6. AnyRef
7. Any

Implicitly

1. by any2stringadd
2. by StringFormat
3. by Ensuring
4. by ArrowAssoc

1. Hide All
2. Show All

Visibility

1. Public
2. Protected

### Value Members

1.  final def !=(arg0: Any): Boolean
   Definition Classes
     AnyRef → Any
2.  final def ##: Int
   Definition Classes
     AnyRef → Any
3.  def +(other: String): String
   Implicit
     This member is added by an implicit conversion from MemBase[T] toany2stringadd[MemBase[T]] performed by method any2stringadd in scala.Predef.
   Definition Classes
     any2stringadd
4.  def ->[B](y: B): (MemBase[T], B)
   Implicit
     This member is added by an implicit conversion from MemBase[T] toArrowAssoc[MemBase[T]] performed by method ArrowAssoc in scala.Predef.
   Definition Classes
     ArrowAssoc
   Annotations
     @inline()
5.  final def ==(arg0: Any): Boolean
   Definition Classes
     AnyRef → Any
6.  macro def apply(x: UInt, y: Clock): T
7.  macro def apply(x: UInt): T

   Creates a read/write accessor into the memory with dynamic addressing.

   Creates a read/write accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.

8.  macro def apply(x: Int): T

   Creates a read accessor into the memory with static addressing.

   Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.

9.  macro def apply(x: BigInt): T

   Creates a read accessor into the memory with static addressing.

   Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.

10.  final def asInstanceOf[T0]: T0
    Definition Classes
      Any
11.  def circuitName: String
    Definition Classes
      HasId
12.  def clockWarning(sourceInfo: Option[SourceInfo], dir: MemPortDirection): Unit
    Attributes
      protected
13.  def clone(): AnyRef
    Attributes
      protected[lang]
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.CloneNotSupportedException]) @native()
14.  def do_apply(idx: UInt, clock: Clock)(implicit sourceInfo: SourceInfo): T
15.  def do_apply(idx: UInt)(implicit sourceInfo: SourceInfo): T

16.  def do_apply(idx: Int)(implicit sourceInfo: SourceInfo): T

17.  def do_apply(idx: BigInt)(implicit sourceInfo: SourceInfo): T

18.  def do_apply_impl(idx: UInt, clock: Clock, dir: MemPortDirection, warn: Boolean)(implicit sourceInfo: SourceInfo): T
    Attributes
      protected
19.  def do_read(idx: UInt, clock: Clock)(implicit sourceInfo: SourceInfo): T

20.  def do_read(idx: UInt)(implicit sourceInfo: SourceInfo): T

21.  def do_write(idx: UInt, data: T, mask: Seq[Bool], clock: Clock)(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): Unit
22.  def do_write(idx: UInt, data: T, mask: Seq[Bool])(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): Unit
23.  def do_write(idx: UInt, data: T, clock: Clock)(implicit sourceInfo: SourceInfo): Unit

24.  def do_write(idx: UInt, data: T)(implicit sourceInfo: SourceInfo): Unit

25.  def ensuring(cond: (MemBase[T]) => Boolean, msg: => Any): MemBase[T]
    Implicit
      This member is added by an implicit conversion from MemBase[T] toEnsuring[MemBase[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
26.  def ensuring(cond: (MemBase[T]) => Boolean): MemBase[T]
    Implicit
      This member is added by an implicit conversion from MemBase[T] toEnsuring[MemBase[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
27.  def ensuring(cond: Boolean, msg: => Any): MemBase[T]
    Implicit
      This member is added by an implicit conversion from MemBase[T] toEnsuring[MemBase[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
28.  def ensuring(cond: Boolean): MemBase[T]
    Implicit
      This member is added by an implicit conversion from MemBase[T] toEnsuring[MemBase[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
29.  final def eq(arg0: AnyRef): Boolean
    Definition Classes
      AnyRef
30.  def equals(that: Any): Boolean
    Definition Classes
      HasId → AnyRef → Any
31.  def finalize(): Unit
    Attributes
      protected[lang]
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.Throwable])
32.  final def getClass(): Class[_ <: AnyRef]
    Definition Classes
      AnyRef → Any
    Annotations
      @native()
33.  def hasSeed: Boolean

    returns

      Whether either autoName or suggestName has been called

    Definition Classes
      HasId
34.  def hashCode(): Int
    Definition Classes
      HasId → AnyRef → Any
35.  def instanceName: String
    Definition Classes
      HasId → InstanceId
36.  final def isInstanceOf[T0]: Boolean
    Definition Classes
      Any
37.  val length: BigInt
38.  final def ne(arg0: AnyRef): Boolean
    Definition Classes
      AnyRef
39.  final def notify(): Unit
    Definition Classes
      AnyRef
    Annotations
      @native()
40.  final def notifyAll(): Unit
    Definition Classes
      AnyRef
    Annotations
      @native()
41.  def parentModName: String
    Definition Classes
      HasId → InstanceId
42.  def parentPathName: String
    Definition Classes
      HasId → InstanceId
43.  def pathName: String
    Definition Classes
      HasId → InstanceId
44.  macro def read(x: UInt, y: Clock): T

    Creates a read accessor into the memory with dynamic addressing.

    Creates a read accessor into the memory with dynamic addressing. Takes a clock parameter to bind a clock that may be different from the implicit clock. See the class documentation of the memory for more detailed information.

45.  macro def read(x: UInt): T

    Creates a read accessor into the memory with dynamic addressing.

    Creates a read accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.

46.  def suggestName(seed: => String): MemBase.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than `autoSeed`, in that regardless of whether `autoSeed` was called, suggestName will always take precedence.

    seed

      The seed for the name of this component

    returns

      this object

    Definition Classes
      HasId
47.  final def synchronized[T0](arg0: => T0): T0
    Definition Classes
      AnyRef
48.  val t: T
49.  final def toAbsoluteTarget: ReferenceTarget

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Definition Classes
      NamedComponent → InstanceId
50.  final def toNamed: ComponentName

    Returns a FIRRTL ComponentName that references this object

    Returns a FIRRTL ComponentName that references this object

    Definition Classes
      NamedComponent → InstanceId
    Note

      Should not be called until circuit elaboration is complete

51.  final def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    If `root` is defined, the target is a hierarchical path starting from `root`.

    If `root` is not defined, the target is a hierarchical path equivalent to `toAbsoluteTarget`.

    Definition Classes
      NamedComponent
    Note

      If `root` is defined, and has not finished elaboration, this must be called within `atModuleBodyEnd`.

      ,

      The NamedComponent must be a descendant of `root`, if it is defined.

      ,

      This doesn't have special handling for Views.

52.  def toString(): String
    Definition Classes
      AnyRef → Any
53.  final def toTarget: ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object

    Returns a FIRRTL ReferenceTarget that references this object

    Definition Classes
      NamedComponent → InstanceId
    Note

      Should not be called until circuit elaboration is complete

54.  final def wait(): Unit
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.InterruptedException])
55.  final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.InterruptedException])
56.  final def wait(arg0: Long): Unit
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.InterruptedException]) @native()
57.  macro def write(idx: UInt, writeData: T, mask: Seq[Bool], clock: Clock)(implicit evidence: <:<[T, Vec[_]]): Unit

    Creates a masked write accessor into the memory with a clock that may be different from the implicit clock.

    Creates a masked write accessor into the memory with a clock that may be different from the implicit clock.

    idx

      memory element index to write into

    mask

      write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.

    clock

      clock to bind to this accessor

    Note

      this is only allowed if the memory's element data type is a Vec

58.  macro def write(idx: UInt, writeData: T, mask: Seq[Bool])(implicit evidence: <:<[T, Vec[_]]): Unit

    Creates a masked write accessor into the memory.

    Creates a masked write accessor into the memory.

    idx

      memory element index to write into

    mask

      write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.

    Note

      this is only allowed if the memory's element data type is a Vec

59.  macro def write(idx: UInt, data: T, clock: Clock): Unit

    Creates a write accessor into the memory with a clock that may be different from the implicit clock.

    Creates a write accessor into the memory with a clock that may be different from the implicit clock.

    idx

      memory element index to write into

    data

      new data to write

    clock

      clock to bind to this accessor

60.  macro def write(idx: UInt, data: T): Unit

    Creates a write accessor into the memory.

    Creates a write accessor into the memory.

    idx

      memory element index to write into

    data

      new data to write

### Deprecated Value Members

1.  def formatted(fmtstr: String): String
   Implicit
     This member is added by an implicit conversion from MemBase[T] toStringFormat[MemBase[T]] performed by method StringFormat in scala.Predef.
   Definition Classes
     StringFormat
   Annotations
     @deprecated @inline()
   Deprecated

     (Since version 2.12.16) Use `formatString.format(value)` instead of `value.formatted(formatString)`, or use the `f""` string interpolator. In Java 15 and later, `formatted` resolves to the new method in String which has reversed parameters.

2.  def →[B](y: B): (MemBase[T], B)
   Implicit
     This member is added by an implicit conversion from MemBase[T] toArrowAssoc[MemBase[T]] performed by method ArrowAssoc in scala.Predef.
   Definition Classes
     ArrowAssoc
   Annotations
     @deprecated
   Deprecated

     (Since version 2.13.0) Use `->` instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.

### Inherited from SourceInfoDoc

### Inherited from NamedComponent

### Inherited from HasId

### Inherited from InstanceId

### Inherited from AnyRef

### Inherited from Any

### Inherited by implicit conversion any2stringadd fromMemBase[T] to any2stringadd[MemBase[T]]

### Inherited by implicit conversion StringFormat fromMemBase[T] to StringFormat[MemBase[T]]

### Inherited by implicit conversion Ensuring fromMemBase[T] to Ensuring[MemBase[T]]

### Inherited by implicit conversion ArrowAssoc fromMemBase[T] to ArrowAssoc[MemBase[T]]

### Ungrouped

### SourceInfoTransformMacro

These internal methods are not part of the public-facing API!
The equivalent public-facing methods do not have the `do_` prefix or have the same name. Use and look at the documentation for those. If you want left shift, use `<<`, not `do_<<`. If you want conversion to a Seq of Bools look at the `asBools` above, not the one below. Users can safely ignore every method in this group!
🐉🐉🐉 Here be dragons... 🐉🐉🐉
These `do_X` methods are used to enable both implicit passing of SourceInfo while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your designs, are converted to their "hidden", `do_*`, via macro transformations. Without using macros here, only one of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a chained apply as an explicit 'implicit' argument and will throw type errors.
The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method into a call to an internal, hidden `do_*` that takes an explicit SourceInfo by inserting an `implicitly[SourceInfo]` as the explicit argument.