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-  package root
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-  package chisel3

  This package contains the main chisel3 API.

  This package contains the main chisel3 API.

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    root
-  package util

  The util package provides extensions to core chisel for common hardware components and utility functions

  The util package provides extensions to core chisel for common hardware components and utility functions

  Definition Classes
    chisel3
-  package circt
  Definition Classes
    util
-  package experimental
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    util
- Arbiter
- ArbiterIO
- BinaryMemoryFile
- BinaryToGray
- BitPat
- Cat
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- Decoupled
- DecoupledIO
- DeqIO
- EnqIO
- Enum
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- HexMemoryFile
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- IrrevocableIO
- ListLookup
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- LockingRRArbiter
- Log2
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- MemoryFile
- MemoryReadPort
- MemoryReadWritePort
- MemoryWritePort
- MixedVec
- MixedVecInit
- Mux1H
- MuxCase
- MuxLookup
- OHToUInt
- Pipe
- PopCount
- PriorityEncoder
- PriorityEncoderOH
- PriorityMux
- Queue
- QueueIO
- RRArbiter
- ReadyValidIO
- RegEnable
- Reverse
- SRAM
- SRAMInterface
- ShiftRegister
- ShiftRegisters
- SparseVec
- SwitchContext
- UIntToOH
- Valid
- is
- isPow2
- log2Ceil
- log2Down
- log2Floor
- log2Up
- pla
- scanLeftOr
- scanRightOr
- signedBitLength
- simpleClassName
- switch
- unsignedBitLength
-  package random
  Definition Classes
    util

o

chisel3.util

# log2Ceil

###

#### object log2Ceil

Compute the log2 of a Scala integer, rounded up. Useful for getting the number of bits needed to represent some number of states (in - 1). To get the number of bits needed to represent some number n, use log2Ceil(n + 1).

Note: can return zero, and should not be used in cases where it may generate unsupported zero-width wires.

Source
  Math.scala
Example:

1.     log2Ceil(1)  // returns 0
       log2Ceil(2)  // returns 1
       log2Ceil(3)  // returns 2
       log2Ceil(4)  // returns 2

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