chisel6.4.0 < Back
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# Packages

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    root
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  This package contains the main chisel3 API.

  This package contains the main chisel3 API.

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    root
-  package aop
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    chisel3
-  package choice

  This package contains Chisel language definitions for describing configuration options and their accepted values.

  This package contains Chisel language definitions for describing configuration options and their accepted values.

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    chisel3
-  package connectable
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    chisel3
-  package experimental

  Package for experimental features, which may have their API changed, be removed, etc.

  Package for experimental features, which may have their API changed, be removed, etc.

  Because its contents won't necessarily have the same level of stability and support as non-experimental, you must explicitly import this package to use its contents.

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    chisel3
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  The properties package includes functionality related to non-hardware data.

  The properties package includes functionality related to non-hardware data.

  This entire package is currently very experimental, so expect some rough edges and rapid API evolution.

  Definition Classes
    chisel3
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    chisel3
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    chisel3
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  The testers package provides the basic interface for chisel testers.

  The testers package provides the basic interface for chisel testers.

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    chisel3
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  The util package provides extensions to core chisel for common hardware components and utility functions

  The util package provides extensions to core chisel for common hardware components and utility functions

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    chisel3
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c

chisel3

# SyncReadMem

###
Companion object SyncReadMem

#### sealed class SyncReadMem[T <: Data] extends MemBase[T]

A sequential/synchronous-read, sequential/synchronous-write memory.

Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.

Source
  Mem.scala
Note

  when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)

Linear Supertypes
MemBase[T], SourceInfoDoc, NamedComponent, HasId, InstanceId, AnyRef, Any
Type Hierarchy

Ordering

1. Grouped
2. Alphabetic
3. By Inheritance

Inherited

1. SyncReadMem
2. MemBase
3. SourceInfoDoc
4. NamedComponent
5. HasId
6. InstanceId
7. AnyRef
8. Any

Implicitly

1. by any2stringadd
2. by StringFormat
3. by Ensuring
4. by ArrowAssoc

1. Hide All
2. Show All

Visibility

1. Public
2. Protected

### Value Members

1.  final def !=(arg0: Any): Boolean
   Definition Classes
     AnyRef → Any
2.  final def ##: Int
   Definition Classes
     AnyRef → Any
3.  def +(other: String): String
   Implicit
     This member is added by an implicit conversion from SyncReadMem[T] toany2stringadd[SyncReadMem[T]] performed by method any2stringadd in scala.Predef.
   Definition Classes
     any2stringadd
4.  def ->[B](y: B): (SyncReadMem[T], B)
   Implicit
     This member is added by an implicit conversion from SyncReadMem[T] toArrowAssoc[SyncReadMem[T]] performed by method ArrowAssoc in scala.Predef.
   Definition Classes
     ArrowAssoc
   Annotations
     @inline()
5.  final def ==(arg0: Any): Boolean
   Definition Classes
     AnyRef → Any
6.  macro def apply(x: UInt, y: Clock): T
   Definition Classes
     MemBase
7.  macro def apply(x: UInt): T

   Creates a read/write accessor into the memory with dynamic addressing.

   Creates a read/write accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.

   Definition Classes
     MemBase
8.  macro def apply(x: Int): T

   Creates a read accessor into the memory with static addressing.

   Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.

   Definition Classes
     MemBase
9.  macro def apply(x: BigInt): T

   Creates a read accessor into the memory with static addressing.

   Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.

   Definition Classes
     MemBase
10.  final def asInstanceOf[T0]: T0
    Definition Classes
      Any
11.  def circuitName: String
    Definition Classes
      HasId
12.  def clockWarning(sourceInfo: Option[SourceInfo], dir: MemPortDirection): Unit
    Attributes
      protected
    Definition Classes
      MemBase
13.  def clone(): AnyRef
    Attributes
      protected[lang]
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.CloneNotSupportedException]) @native()
14.  def do_apply(idx: UInt, clock: Clock)(implicit sourceInfo: SourceInfo): T
    Definition Classes
      MemBase
15.  def do_apply(idx: UInt)(implicit sourceInfo: SourceInfo): T

    Definition Classes
      MemBase
16.  def do_apply(idx: Int)(implicit sourceInfo: SourceInfo): T

    Definition Classes
      MemBase
17.  def do_apply(idx: BigInt)(implicit sourceInfo: SourceInfo): T

    Definition Classes
      MemBase
18.  def do_apply_impl(idx: UInt, clock: Clock, dir: MemPortDirection, warn: Boolean)(implicit sourceInfo: SourceInfo): T
    Attributes
      protected
    Definition Classes
      MemBase
19.  def do_read(idx: UInt, en: Bool, clock: Clock)(implicit sourceInfo: SourceInfo): T

20.  def do_read(idx: UInt, en: Bool)(implicit sourceInfo: SourceInfo): T

21.  def do_read(idx: UInt)(implicit sourceInfo: SourceInfo): T

    Definition Classes
      SyncReadMem → MemBase
22.  def do_read(idx: UInt, clock: Clock)(implicit sourceInfo: SourceInfo): T

    Definition Classes
      MemBase
23.  def do_readWrite(idx: UInt, writeData: T, mask: Seq[Bool], en: Bool, isWrite: Bool, clock: Clock)(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): T
24.  def do_readWrite(idx: UInt, writeData: T, mask: Seq[Bool], en: Bool, isWrite: Bool)(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): T
25.  def do_readWrite(idx: UInt, data: T, en: Bool, isWrite: Bool, clock: Clock)(implicit sourceInfo: SourceInfo): T

26.  def do_readWrite(idx: UInt, writeData: T, en: Bool, isWrite: Bool)(implicit sourceInfo: SourceInfo): T

27.  def do_write(idx: UInt, data: T, mask: Seq[Bool], clock: Clock)(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): Unit
    Definition Classes
      MemBase
28.  def do_write(idx: UInt, data: T, mask: Seq[Bool])(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): Unit
    Definition Classes
      MemBase
29.  def do_write(idx: UInt, data: T, clock: Clock)(implicit sourceInfo: SourceInfo): Unit

    Definition Classes
      MemBase
30.  def do_write(idx: UInt, data: T)(implicit sourceInfo: SourceInfo): Unit

    Definition Classes
      MemBase
31.  def ensuring(cond: (SyncReadMem[T]) => Boolean, msg: => Any): SyncReadMem[T]
    Implicit
      This member is added by an implicit conversion from SyncReadMem[T] toEnsuring[SyncReadMem[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
32.  def ensuring(cond: (SyncReadMem[T]) => Boolean): SyncReadMem[T]
    Implicit
      This member is added by an implicit conversion from SyncReadMem[T] toEnsuring[SyncReadMem[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
33.  def ensuring(cond: Boolean, msg: => Any): SyncReadMem[T]
    Implicit
      This member is added by an implicit conversion from SyncReadMem[T] toEnsuring[SyncReadMem[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
34.  def ensuring(cond: Boolean): SyncReadMem[T]
    Implicit
      This member is added by an implicit conversion from SyncReadMem[T] toEnsuring[SyncReadMem[T]] performed by method Ensuring in scala.Predef.
    Definition Classes
      Ensuring
35.  final def eq(arg0: AnyRef): Boolean
    Definition Classes
      AnyRef
36.  def equals(that: Any): Boolean
    Definition Classes
      HasId → AnyRef → Any
37.  def finalize(): Unit
    Attributes
      protected[lang]
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.Throwable])
38.  final def getClass(): Class[_ <: AnyRef]
    Definition Classes
      AnyRef → Any
    Annotations
      @native()
39.  def hasSeed: Boolean

    returns

      Whether either autoName or suggestName has been called

    Definition Classes
      HasId
40.  def hashCode(): Int
    Definition Classes
      HasId → AnyRef → Any
41.  def instanceName: String
    Definition Classes
      HasId → InstanceId
42.  final def isInstanceOf[T0]: Boolean
    Definition Classes
      Any
43.  val length: BigInt
    Definition Classes
      MemBase
44.  final def ne(arg0: AnyRef): Boolean
    Definition Classes
      AnyRef
45.  final def notify(): Unit
    Definition Classes
      AnyRef
    Annotations
      @native()
46.  final def notifyAll(): Unit
    Definition Classes
      AnyRef
    Annotations
      @native()
47.  def parentModName: String
    Definition Classes
      HasId → InstanceId
48.  def parentPathName: String
    Definition Classes
      HasId → InstanceId
49.  def pathName: String
    Definition Classes
      HasId → InstanceId
50.  macro def read(idx: UInt, en: Bool, clock: Clock): T
51.  macro def read(x: UInt, en: Bool): T
52.  macro def read(x: UInt): T

    Creates a read accessor into the memory with dynamic addressing.

    Creates a read accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.

    Definition Classes
      SyncReadMem → MemBase
53.  macro def read(x: UInt, y: Clock): T

    Creates a read accessor into the memory with dynamic addressing.

    Creates a read accessor into the memory with dynamic addressing. Takes a clock parameter to bind a clock that may be different from the implicit clock. See the class documentation of the memory for more detailed information.

    Definition Classes
      MemBase
54.  val readUnderWrite: ReadUnderWrite
55.  macro def readWrite(idx: UInt, writeData: T, mask: Seq[Bool], en: Bool, isWrite: Bool, clock: Clock)(implicit evidence: <:<[T, Vec[_]]): T

    Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element and a clock that may be different from the implicit clock.

    Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element and a clock that may be different from the implicit clock.

    idx

      memory element index to write into

    writeData

      new data to write

    mask

      the write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.

    isWrite

      performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true

    clock

      clock to bind to this read-write port

    returns

      The read data Vec of the memory at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle

    Note

      this is only allowed if the memory's element data type is a Vec

56.  macro def readWrite(idx: UInt, writeData: T, mask: Seq[Bool], en: Bool, isWrite: Bool)(implicit evidence: <:<[T, Vec[_]]): T

    Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element.

    Generates an explicit read-write port for this SyncReadMem, with a bytemask for performing partial writes to a Vec element.

    idx

      memory element index to write into

    writeData

      new data to write

    mask

      the write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.

    isWrite

      performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true

    returns

      The read data Vec of the memory at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle

    Example:

    1. Controlling a read/masked write port with IO signals

           class MyMaskedMemWrapper extends Module {
             val width = 2

             val io = IO(new Bundle {
               val address = Input(UInt())
               val wdata = Input(Vec(2, UInt(width.W)))
               val mask = Input(Vec(2, Bool()))
               val enable = Input(Bool())
               val isWrite = Input(Bool())
               val rdata = Output(Vec(2, UInt(width.W)))
             })

             val mem = SyncReadMem(2, Vec(2, UInt(width.W)))
             io.rdata := mem.readWrite(io.address, io.wdata, io.mask, io.enable, io.isWrite)
           }

    Note

      this is only allowed if the memory's element data type is a Vec

57.  macro def readWrite(idx: UInt, writeData: T, en: Bool, isWrite: Bool, clock: Clock): T

    Generates an explicit read-write port for this SyncReadMem, using a clock that may be different from the implicit clock.

    Generates an explicit read-write port for this SyncReadMem, using a clock that may be different from the implicit clock.

    idx

      memory element index to write into

    writeData

      new data to write

    isWrite

      performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true

    clock

      clock to bind to this read-write port

    returns

      The read data of the memory, which gives the value at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle.

58.  macro def readWrite(idx: UInt, writeData: T, en: Bool, isWrite: Bool): T

    Generates an explicit read-write port for this SyncReadMem.

    Generates an explicit read-write port for this SyncReadMem. Note that this does not infer port directionality based on connection semantics and the `when` context unlike SyncReadMem.apply(), so the behavior of the port must be controlled by changing the values of the input parameters.

    idx

      memory element index to write into

    writeData

      new data to write

    isWrite

      performs a write instead of a read when enable is true; the return value becomes undefined when this parameter is true

    returns

      The read data of the memory, which gives the value at idx when enable is true and isWrite is false, or an undefined value otherwise, on the following clock cycle.

    Example:

    1. Controlling a read/write port with IO signals

           class MyMemWrapper extends Module {
             val width = 2

             val io = IO(new Bundle {
               val address = Input(UInt())
               val wdata = Input(UInt(width.W))
               val enable = Input(Bool())
               val isWrite = Input(Bool())
               val rdata = Output(UInt(width.W))
             })

             val mem = SyncReadMem(2, UInt(width.W))
             io.rdata := mem.readWrite(io.address, io.wdata, io.enable, io.isWrite)
           }

59.  def suggestName(seed: => String): SyncReadMem.this.type

    Takes the first seed suggested.

    Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.

    Is a higher priority than `autoSeed`, in that regardless of whether `autoSeed` was called, suggestName will always take precedence.

    seed

      The seed for the name of this component

    returns

      this object

    Definition Classes
      HasId
60.  final def synchronized[T0](arg0: => T0): T0
    Definition Classes
      AnyRef
61.  val t: T
    Definition Classes
      MemBase
62.  final def toAbsoluteTarget: ReferenceTarget

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph

    Definition Classes
      NamedComponent → InstanceId
63.  final def toNamed: ComponentName

    Returns a FIRRTL ComponentName that references this object

    Returns a FIRRTL ComponentName that references this object

    Definition Classes
      NamedComponent → InstanceId
    Note

      Should not be called until circuit elaboration is complete

64.  final def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    Returns a FIRRTL ReferenceTarget that references this object, relative to an optional root.

    If `root` is defined, the target is a hierarchical path starting from `root`.

    If `root` is not defined, the target is a hierarchical path equivalent to `toAbsoluteTarget`.

    Definition Classes
      NamedComponent
    Note

      If `root` is defined, and has not finished elaboration, this must be called within `atModuleBodyEnd`.

      ,

      The NamedComponent must be a descendant of `root`, if it is defined.

      ,

      This doesn't have special handling for Views.

65.  def toString(): String
    Definition Classes
      AnyRef → Any
66.  final def toTarget: ReferenceTarget

    Returns a FIRRTL ReferenceTarget that references this object

    Returns a FIRRTL ReferenceTarget that references this object

    Definition Classes
      NamedComponent → InstanceId
    Note

      Should not be called until circuit elaboration is complete

67.  final def wait(): Unit
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.InterruptedException])
68.  final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.InterruptedException])
69.  final def wait(arg0: Long): Unit
    Definition Classes
      AnyRef
    Annotations
      @throws(classOf[java.lang.InterruptedException]) @native()
70.  macro def write(idx: UInt, writeData: T, mask: Seq[Bool], clock: Clock)(implicit evidence: <:<[T, Vec[_]]): Unit

    Creates a masked write accessor into the memory with a clock that may be different from the implicit clock.

    Creates a masked write accessor into the memory with a clock that may be different from the implicit clock.

    idx

      memory element index to write into

    mask

      write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.

    clock

      clock to bind to this accessor

    Definition Classes
      MemBase
    Note

      this is only allowed if the memory's element data type is a Vec

71.  macro def write(idx: UInt, writeData: T, mask: Seq[Bool])(implicit evidence: <:<[T, Vec[_]]): Unit

    Creates a masked write accessor into the memory.

    Creates a masked write accessor into the memory.

    idx

      memory element index to write into

    mask

      write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.

    Definition Classes
      MemBase
    Note

      this is only allowed if the memory's element data type is a Vec

72.  macro def write(idx: UInt, data: T, clock: Clock): Unit

    Creates a write accessor into the memory with a clock that may be different from the implicit clock.

    Creates a write accessor into the memory with a clock that may be different from the implicit clock.

    idx

      memory element index to write into

    data

      new data to write

    clock

      clock to bind to this accessor

    Definition Classes
      MemBase
73.  macro def write(idx: UInt, data: T): Unit

    Creates a write accessor into the memory.

    Creates a write accessor into the memory.

    idx

      memory element index to write into

    data

      new data to write

    Definition Classes
      MemBase

### Deprecated Value Members

1.  def formatted(fmtstr: String): String
   Implicit
     This member is added by an implicit conversion from SyncReadMem[T] toStringFormat[SyncReadMem[T]] performed by method StringFormat in scala.Predef.
   Definition Classes
     StringFormat
   Annotations
     @deprecated @inline()
   Deprecated

     (Since version 2.12.16) Use `formatString.format(value)` instead of `value.formatted(formatString)`, or use the `f""` string interpolator. In Java 15 and later, `formatted` resolves to the new method in String which has reversed parameters.

2.  def →[B](y: B): (SyncReadMem[T], B)
   Implicit
     This member is added by an implicit conversion from SyncReadMem[T] toArrowAssoc[SyncReadMem[T]] performed by method ArrowAssoc in scala.Predef.
   Definition Classes
     ArrowAssoc
   Annotations
     @deprecated
   Deprecated

     (Since version 2.13.0) Use `->` instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.

### Inherited from MemBase[T]

### Inherited from SourceInfoDoc

### Inherited from NamedComponent

### Inherited from HasId

### Inherited from InstanceId

### Inherited from AnyRef

### Inherited from Any

### Inherited by implicit conversion any2stringadd fromSyncReadMem[T] to any2stringadd[SyncReadMem[T]]

### Inherited by implicit conversion StringFormat fromSyncReadMem[T] to StringFormat[SyncReadMem[T]]

### Inherited by implicit conversion Ensuring fromSyncReadMem[T] to Ensuring[SyncReadMem[T]]

### Inherited by implicit conversion ArrowAssoc fromSyncReadMem[T] to ArrowAssoc[SyncReadMem[T]]

### Ungrouped

### SourceInfoTransformMacro

These internal methods are not part of the public-facing API!
The equivalent public-facing methods do not have the `do_` prefix or have the same name. Use and look at the documentation for those. If you want left shift, use `<<`, not `do_<<`. If you want conversion to a Seq of Bools look at the `asBools` above, not the one below. Users can safely ignore every method in this group!
🐉🐉🐉 Here be dragons... 🐉🐉🐉
These `do_X` methods are used to enable both implicit passing of SourceInfo while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your designs, are converted to their "hidden", `do_*`, via macro transformations. Without using macros here, only one of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a chained apply as an explicit 'implicit' argument and will throw type errors.
The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method into a call to an internal, hidden `do_*` that takes an explicit SourceInfo by inserting an `implicitly[SourceInfo]` as the explicit argument.