chisel6.4.0 < Back
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# Packages

-  package root
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    root
-  package circt
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    root
-  package stage
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    circt
-  package phases
  Definition Classes
    stage
- CIRCTOption
- CIRCTOptions
- CIRCTOptionsView
- CIRCTTarget
- CIRCTTargetAnnotation
- CLI
- ChiselMain
- ChiselStage
- EmittedMLIR
- FirtoolBinaryPath
- FirtoolOption
- PreserveAggregate

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circt.stage

# ChiselStage

###
Companion class ChiselStage

#### object ChiselStage

Utilities for compiling Chisel

Source
  ChiselStage.scala

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### Value Members

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6.  def convert(gen: => RawModule, args: Array[String] = Array.empty): Circuit

   Return a CHIRRTL circuit for a Chisel module

   Return a CHIRRTL circuit for a Chisel module

   gen

     a call-by-name Chisel module

7.  def emitCHIRRTL(gen: => RawModule, args: Array[String] = Array.empty): String

   Elaborate a Chisel circuit into a CHIRRTL string

8.  def emitFIRRTLDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

   Compile a Chisel circuit to FIRRTL dialect

9.  def emitHWDialect(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

   Compile a Chisel circuit to HWS dialect

10.  def emitSystemVerilog(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): String

    Compile a Chisel circuit to SystemVerilog

    Compile a Chisel circuit to SystemVerilog

    gen

      a call-by-name Chisel module

    args

      additional command line arguments to pass to Chisel

    firtoolOpts

      additional circt.stage.FirtoolOption to pass to firtool

    returns

      a string containing the Verilog output

11.  def emitSystemVerilogFile(gen: => RawModule, args: Array[String] = Array.empty, firtoolOpts: Array[String] = Array.empty): AnnotationSeq

    Compile a Chisel circuit to SystemVerilog with file output

    Compile a Chisel circuit to SystemVerilog with file output

    gen

      a call-by-name Chisel module

    args

      additional command line arguments to pass to Chisel

    firtoolOpts

      additional command line options to pass to firtool

    returns

      a string containing the Verilog output

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### Inherited from Any

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