chisel6.4.0 < Back
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# Packages

-  package root
  Definition Classes
    root
-  package chisel3

  This package contains the main chisel3 API.

  This package contains the main chisel3 API.

  Definition Classes
    root
-  package util

  The util package provides extensions to core chisel for common hardware components and utility functions

  The util package provides extensions to core chisel for common hardware components and utility functions

  Definition Classes
    chisel3
-  package experimental
  Definition Classes
    util
-  package decode
  Definition Classes
    experimental
- BitSet
- BoringUtils
- BoringUtilsException
- FlattenInstance
- ForceNameAnnotation
- InlineInstance
- forceName
- getAnnotations
- loadMemoryFromFile
- loadMemoryFromFileInline

o

chisel3.util.experimental

# loadMemoryFromFileInline

###

#### object loadMemoryFromFileInline

loadMemoryFromFileInline is an annotation generator that helps with loading a memory from a text file inlined in the Verilog module. This relies on Verilator and Verilog's `$readmemh` or `$readmemb`.

This annotation, when the FIRRTL compiler runs, triggers the `MemoryFileInlineAnnotation` that will add Verilog directives inlined to the module enabling the specified memories to be initialized from files. The module supports both `hex` and `bin` files by passing the appropriate `MemoryLoadFileType.FileType` `argument with `MemoryLoadFileType.Hex` or` MemoryLoadFileType.Binary`. Hex is the default.`

#### Example module

Consider a simple Module containing a memory:

    import chisel3._
    class UsesMem(memoryDepth: Int, memoryType: Data) extends Module {
      val io = IO(new Bundle {
        val address = Input(UInt(memoryType.getWidth.W))
        val value   = Output(memoryType)
      })
      val memory = Mem(memoryDepth, memoryType)
      io.value := memory(io.address)
    }

#### Above module with annotation

To load this memory from the file `/workspace/workdir/mem1.hex.txt` just add an import and annotate the memory:

    import chisel3._
    import chisel3.util.experimental.loadMemoryFromFileInline   // <<-- new import here
    class UsesMem(memoryDepth: Int, memoryType: Data) extends Module {
      val io = IO(new Bundle {
        val address = Input(UInt(memoryType.getWidth.W))
        val value   = Output(memoryType)
      })
      val memory = Mem(memoryDepth, memoryType)
      io.value := memory(io.address)
      loadMemoryFromFileInline(memory, "/workspace/workdir/mem1.hex.txt")  // <<-- Note the annotation here
    }

#### Example file format

A memory file should consist of ASCII text in either hex or binary format. The following example shows such a file formatted to use hex:

     0
     7
     d
    15

A binary file can be similarly constructed. Chisel does not validate the file format or existence. It is supposed to be in a path accessible by the synthesis tool together with the generated Verilog.

Source
  LoadMemoryTransform.scala
See also

  Chisel3 Wiki entry on "Loading Memories in Simulation"

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4.  def apply[T <: Data](memory: MemBase[T], fileName: String, hexOrBinary: FileType = MemoryLoadFileType.Hex): Unit

   Annotate a memory such that it can be initialized inline using a file

   Annotate a memory such that it can be initialized inline using a file

   memory

     the memory

   fileName

     the file used for initialization

   hexOrBinary

     whether the file uses a hex or binary number representation

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