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  This package contains the main chisel3 API.

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  The util package provides extensions to core chisel for common hardware components and utility functions

  The util package provides extensions to core chisel for common hardware components and utility functions

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o

chisel3.util

# SRAM

###

#### object SRAM

Source
  SRAM.scala

Linear Supertypes
AnyRef, Any
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1. SRAM
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### Value Members

1.  final def !=(arg0: Any): Boolean
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     AnyRef → Any
2.  final def ##: Int
   Definition Classes
     AnyRef → Any
3.  final def ==(arg0: Any): Boolean
   Definition Classes
     AnyRef → Any
4.  def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

     The data type of the memory element

   size

     The desired size of the inner `SyncReadMem`

   memoryFile

     A memory file whose path is emitted as Verilog directives to initialize the inner `SyncReadMem`

   returns

     A new `SRAMInterface` wire containing the control signals for each instantiated port

   Note

     This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

     ,

     Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

5.  def apply[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

     The data type of the memory element

   size

     The desired size of the inner `SyncReadMem`

   returns

     A new `SRAMInterface` wire containing the control signals for each instantiated port

   Note

     This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

     ,

     Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

6.  def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

     The data type of the memory element

   size

     The desired size of the inner `SyncReadMem`

   numReadPorts

     The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

   numWritePorts

     The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

   numReadwritePorts

     The number of desired read/write ports >= 0, and the above two conditions must hold

   memoryFile

     A memory file whose path is emitted as Verilog directives to initialize the inner `SyncReadMem`

   returns

     A new `SRAMInterface` wire containing the control signals for each instantiated port

   Note

     This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

     ,

     Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

7.  def apply[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit sourceInfo: SourceInfo): SRAMInterface[T]

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports.

   Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

   T

     The data type of the memory element

   size

     The desired size of the inner `SyncReadMem`

   numReadPorts

     The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

   numWritePorts

     The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

   numReadwritePorts

     The number of desired read/write ports >= 0, and the above two conditions must hold

   returns

     A new `SRAMInterface` wire containing the control signals for each instantiated port

   Note

     This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

     ,

     Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

8.  final def asInstanceOf[T0]: T0
   Definition Classes
     Any
9.  def clone(): AnyRef
   Attributes
     protected[lang]
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10.  final def eq(arg0: AnyRef): Boolean
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11.  def equals(arg0: AnyRef): Boolean
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12.  def finalize(): Unit
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13.  final def getClass(): Class[_ <: AnyRef]
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14.  def hashCode(): Int
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15.  final def isInstanceOf[T0]: Boolean
    Definition Classes
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16.  def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock], memoryFile: MemoryFile)(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit `Clock`, rather than being given the implicit clock.

    T

      The data type of the memory element

    size

      The desired size of the inner `SyncReadMem`

    readPortClocks

      A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

    writePortClocks

      A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

    readwritePortClocks

      A sequence of clocks for each read-write port; and the above two conditions must hold

    memoryFile

      A memory file whose path is emitted as Verilog directives to initialize the inner `SyncReadMem`

    returns

      A new `SRAMInterface` wire containing the control signals for each instantiated port

    Note

      The size of each `Clock` sequence determines the corresponding number of read, write, and read-write ports

      ,

      This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

      ,

      Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

17.  def masked[T <: Data](size: BigInt, tpe: T, readPortClocks: Seq[Clock], writePortClocks: Seq[Clock], readwritePortClocks: Seq[Clock])(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. Each port is clocked with its own explicit `Clock`, rather than being given the implicit clock.

    T

      The data type of the memory element

    size

      The desired size of the inner `SyncReadMem`

    readPortClocks

      A sequence of clocks for each read port; and (numReadPorts + numReadwritePorts) > 0

    writePortClocks

      A sequence of clocks for each write port; and (numWritePorts + numReadwritePorts) > 0

    readwritePortClocks

      A sequence of clocks for each read-write port; and the above two conditions must hold

    returns

      A new `SRAMInterface` wire containing the control signals for each instantiated port

    Note

      The size of each `Clock` sequence determines the corresponding number of read, write, and read-write ports

      ,

      This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

      ,

      Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

18.  def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int, memoryFile: MemoryFile)(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

    T

      The data type of the memory element

    size

      The desired size of the inner `SyncReadMem`

    numReadPorts

      The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

    numWritePorts

      The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

    numReadwritePorts

      The number of desired read/write ports >= 0, and the above two conditions must hold

    memoryFile

      A memory file whose path is emitted as Verilog directives to initialize the inner `SyncReadMem`

    returns

      A new `SRAMInterface` wire containing the control signals for each instantiated port

    Note

      This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

      ,

      Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

19.  def masked[T <: Data](size: BigInt, tpe: T, numReadPorts: Int, numWritePorts: Int, numReadwritePorts: Int)(implicit evidence: <:<[T, Vec[_]], sourceInfo: SourceInfo): SRAMInterface[T]

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports.

    Generates a SyncReadMem within the current module, connected to an explicit number of read, write, and read/write ports, with masking capability on all write and read/write ports. This SRAM abstraction has both read and write capabilities: that is, it contains at least one read accessor (a read-only or read-write port), and at least one write accessor (a write-only or read-write port).

    T

      The data type of the memory element

    size

      The desired size of the inner `SyncReadMem`

    numReadPorts

      The number of desired read ports >= 0, and (numReadPorts + numReadwritePorts) > 0

    numWritePorts

      The number of desired write ports >= 0, and (numWritePorts + numReadwritePorts) > 0

    numReadwritePorts

      The number of desired read/write ports >= 0, and the above two conditions must hold

    returns

      A new `SRAMInterface` wire containing the control signals for each instantiated port

    Note

      This does *not* return the `SyncReadMem` itself, you must interact with it using the returned bundle

      ,

      Read-only memories (R >= 1, W === 0, RW === 0) and write-only memories (R === 0, W >= 1, RW === 0) are not supported by this API, and will result in an error if declared.

20.  final def ne(arg0: AnyRef): Boolean
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21.  final def notify(): Unit
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22.  final def notifyAll(): Unit
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23.  final def synchronized[T0](arg0: => T0): T0
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24.  def toString(): String
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25.  final def wait(): Unit
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26.  final def wait(arg0: Long, arg1: Int): Unit
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27.  final def wait(arg0: Long): Unit
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